The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for intelligent certificate discovery in physical and virtualized networks.
Peripheral Component Interconnect (PCI) devices have a set of registers referred to as configuration space and PCI Express (PCIe) introduces extended configuration space for PCIe devices. Configuration space registers are mapped to memory locations. Device drivers and diagnostic software must have access to the configuration space, and operating systems typically use Application Program Interfaces (APIs) to allow access to device configuration space. When the operating system does not have access methods defined or APIs for memory mapped configuration space requests, the driver or diagnostic software has the burden to access the configuration space in a manner that is compatible with the operating system's underlying access rules. In all systems, device drivers are encouraged to use APIs provided by the operating system to access the configuration space of the device.
To address a PCIe device, the PCIe device must be enabled by being mapped into the system's Input/Output (I/O) port address space or memory-mapped address space. The Basic Input/Output System (BIOS) programs the Base Address Registers (commonly called BARs) to inform the device of its address mapping by writing configuration commands to the PCI controller. Because all PCIe devices are in an inactive state upon system reset, they will have no addresses assigned to them by which the operating system or device drivers can communicate with them. The BIOS geographically addresses the PCI slots (for example, the first PCIe slot, the second PCIe slot, or the third PCIe slot, etc., on the motherboard) through the PCI controller using per slot Initialization Device Select (IDSEL) signals.
Since there is no direct method for the BIOS to determine which PCI slots have devices installed (nor which functions the device implements) the PCI bus(es) must be enumerated. Bus enumeration is performed by attempting to read the Device ID (DID) register and Vendor ID (VID) register for each combination of bus number and PCIe device number at the device's function #0. Note that device number, different from DID, is merely a device's sequential number on that bus, moreover, after a new bridge a new bus number is defined and device enumeration restart by zero.
If no response is received from the device's function #0, the bus master performs an abort and returns an all-bits-on value (FFFFFFFF in hexadecimal), which is an invalid VID/DID value, thus a device driver can tell that the specified combination bus/device_number/function (B/D/F) is not present. So, when a read to a function ID of zero for a given bus/device causes the master (initiator) to abort, it must then be presumed that no working device exists on that bus because devices are required to implement function number zero. In this case, reads to the remaining functions numbers (1-7) are not necessary as they also will not exist.
When a read to a specified B/D/F combination for the vendor ID register succeeds, the PCI controller knows that the PCIe device exists. Thus, the PCI Controller writes all ones to its BARs and reads back the PCIe device's requested memory size in an encoded form. The design implies that all address space sizes are a power of two and are naturally aligned.
At this point, the BIOS programs the memory-mapped and I/O port addresses into the PCIe device's BAR configuration register. These addresses stay valid as long as the system remains turned on. Upon power-off or system reset, all these settings are lost and the procedure is repeated next time the system is powered back on. Since this entire process is fully automated, the user is spared the task of configuring any newly added hardware manually by changing dual in-line package (DIP) switches on the cards themselves. This automatic device discovery and address space assignment is how plug and play is implemented.